As the trend in miniaturizing of the integrated circuit (IC) continues, the need for wafer thinning technology will increase. To fully appreciate this need, it is necessary to consider the common and generally accepted phenomena that most, if not all ICs, perform at less than ideal and produce heat as a by product of their function. In a conventional IC, only a minor proportion of the substrate is used for its semiconductor performance. Since semiconductors are poor thermal conductors, they will store the generated heat in their mass. As more heat is produced, more is stored, until a metaphysical limit is reached in the electrical circuit at which efficiencies drop and errors occur. To maintain proper IC function, heat must be continually removed as it is generated.
The common method for IC cooling (i.e. heat removal) is to install blowers which dissipate heat from the printed wire board (PWB). For miniaturized ICs, this means of removing heat is impractical. Hand-held devices such as calculators, cell phones, pagers, and others must depend upon dissipation of heat through conduction. For best results, the IC′ substrate is thinned and brought into direct contact with a heat conducting medium, e.g. heat sink. As the IC′ heat is generated, it is conducted away (dissipated) by intimate contact with a comparatively large heat sink.
Not only does wafer thinning help to dissipate heat, but it also aids in the electrical operation of the IC. Substrate thickness affects impedance and capacitative performance of certain connecting leads, e.g. transmission lines, of given thickness from the top of the IC to the bottom where contact is made to the PWB. Thick substrates cause an increase in capacitance, requiring thicker transmission lines, and in turn, a larger IC footprint. Substrate thinning increases impedance while capacitance decreases, causing a reduction in transmission line thickness, and in turn, a reduction in IC size. In other words, substrate thinning facilitates IC miniaturization.
An additional incentive in support of substrate thinning involves geometrical reasons. Via-holes are etched on the backside to facilitate frontside contacts. In order to construct a via-hole (hereafter sometimes referred to as a “Via” or “Vias”) using common dry-etch techniques, minimum geometrical design standards apply. Namely, for substrate thicknesses of <100 um, a 30–70 um diameter via is constructed using dry-etch methods that produce minimal post-etch residue within an acceptable time. For thick substrates, larger diameter vias will be needed, requiring longer dry etch times, producing greater amounts of post-etch residue, resulting in a significant reduction in throughput. Larger vias require more metalization and in turn, higher cost. Therefore, from the standpoint of backside processing, thin substrates can be processed quicker and at lower cost.
A final consideration in support of thin substrates is that they are more easily cut and scribed into ICs. Thinner substrates have a smaller amount of material to penetrate and cut, and therefore require less effort. Whether the method used is sawing, scribe and break, or laser ablation, ICs are easier to cut from thinner substrates.
Most semiconductor wafers are thinned after frontside operations. For ease of handling, wafers are processed (i.e. frontside devices) at their normal full-size thickness, e.g. 600–700 um (0.024–0.028″). Once completed, they are thinned to 100–150 um (0.004–0.006″). In some cases, as in hybrid substrates used for high power devices, e.g. Gallium Arsenide (GaAs), thickness may be taken down to 25 um (0.001″).
Mechanical substrate thinning is performed by bringing the wafer surface in contact with a hard and flat rotating horizontal platter that contains a liquid slurry. The slurry may contain abrasive media with chemical etchants such as ammonia, fluoride, or the combinations thereof. The abrasive operates as a “gross” substrate removal means, i.e. thinning, while the etchant chemistry facilitates “polishing” at the submicron level. The wafer is maintained in contact with the media until an amount of substrate has been removed to achieve a targeted thickness. For a wafer thickness of 300 um or greater, the wafer is held in place with tooling that utilizes a vacuum chuck or some means of mechanical attachment. When wafer thickness is reduced to <300 um, it becomes difficult or impossible to maintain control, e.g. attachment and handling, of the wafer. In some cases, mechanical devices may be made to attach and hold onto thinned wafers, however, they are subject to many problems, especially when processes may vary. For this reason, the wafers are mounted onto a separate rigid (carrier) substrate. This substrate becomes the holding platform for further thinning and post-thinned processing.
Carrier substrates vary between sapphire, quartz, certain glasses, and silicon, and usually exhibit a thickness of 1000 um (1 mm or 0.040″). Substrate choice will depend on how closely matched the coefficient of thermal expansion (CLTE) is between each material.
Since the adhesive becomes incorporated into the wafer-carrier package (wafer package), its properties must include the fundamental criteria of thermal stability. The adhesive must maintain a rigid network over the temperature program of the process such that no mechanical compromise occurs and any reference points established during mounting will be preserved. The maximum temperature exhibited in wafer backside processing occurs during resist baking and via etching. For GaAs processing, these temperatures are typically ≦130° C.
Another desire of the adhesive is to exhibit good chemical resistance. This must be established for a range of chemistries from strong etchants used in post-thinning stress relief such as sulfuric, ammonia, and/or peroxide, as well as organic solvents used in the lithography and clean steps during via-hole processing. Ideally, the adhesive must be resistant to these process chemistries, yet be selectively dissolved and removed at the end of the manufacturing process line. At times, certain aggressive chemistries may be chosen which have detrimental effects on the adhesive. As such, some temporary manufacturing measures may be taken to include protective tape or other wafer coverings.
From the foregoing described regimen, it is seen that a need exists for an adhesive which: can achieve a planarized and uniform substrate coating; can be mounted to rigid substrates; and is able to withstand the thermal and chemical rigors in a robust yet selective manner to support final removal and cleansing of the wafer. The invention provides an adhesive system that when used at selected process parameters and conditions, affords a mechanism that lends substantial practical support for wafer thinning and backside processing operations.